The present invention relates to a new fabricating method of flash memory and, more particularly, to a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell. The manufacturing process of floating gate can be completed in automatic alignment way without any extra mask process, thereby fabricating a flash memory device with 2bit/cell.
In the present information society, electrically erasable and programmable read only memories (EEPROMs) are widely adopted as memory devices of electronic products. Conventional EEPROMs have the drawback of slower speed of access. However, along with progress of processing technology, EEPROMs with faster speed of access, generally called flash memories, have been developed. This new kind of nonvolatile memories can improve the drawbacks of conventional memories.
Basically, conventional flash memories are nonvolatile memories with floating gate transistors as the basis. As shown in FIG. 1, in each memory cell of flash memory, a source 12 and a drain 14 are formed in a semiconductor substrate 10 by means of ion implantation, respectively. Next, a dielectric layer 16, a floating gate 18 for charge storage, an insulating dielectric 20, and a control gate 22 for control of data access are formed in order from bottom to top on the surface of the semiconductor substrate 10 between the source 12 and the drain 14. The memory state of the flash memory depends on the charge density of the floating gate 18, and the operation thereof depends on the technique of injecting charges into or removing charges from the floating gate.
When program data is written in, a high voltage is applied to the control gate to let hot electrons pass through the dielectric layer 16 from the drain 14 and be injected into the floating gate 18, hence enhancing the threshold voltage. When erasing data, a high voltage is applied to the source 12 to let the above electrons injected into the floating gate 18 pass through the dielectric layer 16 and then flow into the source by means of the Fowler-Nordheim tunneling effect, hence restoring to the original threshold voltage.
However, in the above nonvolatile flash memory, each memory cell can only store a bit. The memory capacity of the conventional flash memory is thus not satisfactory. Accordingly, in order to resolve the drawback of too small memory capacity of conventional flash memories, the present invention provides a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell, wherein discontinuous floating gates are fabricated below the control gate to build a flash memory with 2bit/cell for increasing the memory capacity of flash memory devices.
The primary object of the present invention is to provide a fabricating method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell, whereby each memory cell in a flash memory has two floating gates as dual-point type charge storage regions, hence doubling the memory capacity of flash memory. Moreover, the two charge storage regions can be controlled through collocation of the source, drain and gate of the device.
Another object of the present invention is to provide a manufacturing method of a flash memory with 2bit/cell, wherein the fabrication process of poly-Si spacers is exploited to complete the fabrication process of floating gates in automatic alignment way without any extra mask process, hence saving the conventional lithography process and resolving the problem of misalignment thereof.
According to the present invention, ion implantation is performed to a silicon substrate having a pad oxide with an already defined silicon nitride as a mask. An oxide is formed and its surface is planarized to remove the silicon nitride and the pad oxide. Next, a tunnel dielectric layer and a first poly-Si layer are deposited on the silicon substrate, and anisotropic etch is then performed to the poly-Si layer to form poly-Si spacers. Finally, an insulating dielectric layer is deposited, and an already defined second poly-Si layer is formed. A flash memory structure with 2bit/cell is thus formed.